1. Field of the Invention
An embodiment of the present invention relates generally to a reconfigurable architecture and, more particularly, to a method, medium, and apparatus that effectively handles an interrupt that occurs during an execution of a task in a reconfigurable array.
2. Description of the Related Art
Traditionally, devices for performing differing operations have been embodied by either fixed hardware or reconfigurable software. For example, when a network controller performing a network interface is embodied/implemented through a computer chip, the network controller is able to perform only the network interface operation defined during the factory fabrication of the computer chip. After the network controller has been fabricated in the factory, changing the desired operation of the network controller is not possible. This is, thus, an example of hardware. Conversely, as a software implementation, for example, a program for implementing a desired operation may be programmed, e.g., for implementation by a general purpose processor. Here, with software, new operations may be performed merely by changing the post-fabrication software. When software is used, various operations may be performed by a given hardware device, but these software implementations have drawbacks in their performing of the desired operations with lower speeds than when only hardware is used.
Thus, to appease the need for speed, and to overcome such hardware drawback, reconfigurable hardware architectures have been designed. These reconfigurable architecture devices can be customized to solve any problem through a hardware implementation, after device fabrication, while still exploiting a large degree of spatially customized computations in order to perform their desired operations.
FIG. 1 illustrates a field programmable gate array (FPGA) as an example of a conventional reconfigurable architecture device. As illustrated in FIG. 1, the FPGA includes a plurality of arithmetic and logic units (ALUs) 101, 102, 103, 104, and 105 and a plurality of lines 106 connecting the plurality of ALUs. The FPGA is customized, during manufacture, to perform some computation, e.g., to compute “A*x*x+B*X+C”. Here, if the operation of “A*x*x+B*X+C” occurs frequently, the FPGA is manufactured in a manner to perform the operation, thereby more quickly performing the same operation than software implemented techniques. After manufacture, the configuration within the FPGA may be changed by applying a current to the lines 106 of the ALUs and designating the ALUs and corresponding interconnections to perform a new operation, e.g., the configuration for computing this alternate operation can be newly formed using plurality of lines 106. As described above, this reconfigurable architecture is architecture capable of performing a new operation by changing the hardware configuration after fabrication.
In FIG. 1, data is input to an ALU one bit at a time. This kind of reconfigurable architecture is called a fine grained array. If data is input to a processing element in units of one word at a time, the reconfigurable architecture is called a coarse grained array (CGA).
FIG. 2 illustrates a tightly-coupled coarse grained array architecture.
The coarse grained array 210 may include a plurality of processing elements 211, with each of the plurality of processing elements 211 including an operation unit 212 and a register file 213. The operation unit 212 performs computations, and the register file 213 is a group of registers for temporarily storing data used by the operation unit 212. In the illustrated coarse grained array, and in embodiments of the present invention, the illustrated operation units are illustrated as “FU” representing a “function unit,” i.e., a particular function performing unit. These units have been referred herein as “operation” units, as these units are not meant to be limiting to any particular operation or device described solely herein, i.e., alternative embodiments not described herein for such operation units are equally available.
A configuration memory 220 may further be included for storing information associated with the configuration of the coarse grained array 210. According to the configuration stored in the configuration memory 220, the coarse grained array 210 changes the connection state between processing elements included in the coarse grained array 210. Further, in this conventional architecture, a data memory 230 is located outside the coarse grained array 210 and stores data.
Such reconfigurable arrays, including this coarse grained array 210, may be implemented with cooperation with the CPU of a computing apparatus. Similarly, the reconfigurable array may be used as a coprocessor, an attached processing unit, or a stand-alone processing unit, for example.
In such reconfigurable arrays, when an interrupt occurs, such as a request for an immediate operation to be commenced, during a loop calculation in the reconfigurable array, there often arises an issue of how to handle the interrupt. The interrupt may further include a hardware interrupt, such as an external I/O unit or a timer, an exception such as undefined instruction, and a software interrupt such as a system call. Typically, when an interrupt request occurs in a general computer architecture, a current context including currently stored values are stored in a memory, processing according to the interrupt is performed, the context stored in the memory is then restored, and the original operations are restarted. Namely, if an interrupt request occurs, a context switching may be required. The “context” represents a current state and condition of a system and may include values stored in a register.
However, using the above FIG. 2 example again, since the coarse grained array includes so many register files, the amount of memory overhead becomes very large. Namely, it takes a relatively long time to store all the values stored in the many register files to a memory. Further, the overall design becomes very complex to provide the line connecting each of the register files to a data memory. As described above, conventional systems to not provide any solutions for the considerable overhead occurring in the coarse grained array when implementing the interrupt requiring the context switch. Particularly, such considerations become even more critical when the process to be performed by an interrupt has a particular constraint, such as having to perform the interrupt operation in real-time.
Accordingly, there is a desire for a technique to efficiently process an interrupt occurring in a processor having a coarse grained array.